1. Field of the Invention
The present invention relates to the process of trimming photoresist material on semiconductor wafers and, more particularly, to improving photoresist trimming while minimizing critical dimension variation between photoresist lines and maximizing photoresist budget.
2. Description of the Related Art
During semiconductor wafer processing, features of the semiconductor device are defined in a semiconductor wafer using well-known patterning and etching processes. FIG. 1 is a partial cross-sectional view illustrating several conventional layers of a semiconductor wafer 10. As shown, the semiconductor wafer 10 includes a semiconductor substrate 12 formed of, e.g., silicon, that supports intermediate layers 15. Intermediate layers 15, for example, include a first layer 14 formed of either a conductive material (e.g., polysilicon) or a dielectric material (e.g., SiO2, depending on the type of device that is being fabricated). The intermediate layers 15 also may include a second layer 16, such as a hard mask layer or an anti-reflective coating (ARC) layer. For ease of illustration, intermediate layers 15 is shown comprising only two layers, but as is well known in the art, more layers may be provided.
Conventionally, to pattern the intermediate layers 15, a layer of photoresist material 18 is deposited onto the semiconductor wafer 10 over the intermediate layers 15, and then patterned by a suitable process such as photolithography. In general, the semiconductor wafer 10 is exposed to light filtered by a reticle, which is a glass plate patterned with the desired integrated circuit layer features.
After passing through the reticle, the light impinges upon the surface of the photoresist material 18. The light changes the chemical composition of the photoresist material 18 such that a developer can be used to remove either the exposed regions (in the case of positive photoresist materials) or the unexposed regions (in the case of negative photoresist materials) of the photoresist material. In the case of positive photoresist materials, the light changes the structure and chemical properties of the photoresist material creating a number of polymerized photoresist sections. These polymerized photoresist sections are then removed using a solvent in a development process leaving a number of photoresist lines. Thereafter, the wafer is etched to remove the material from the areas that are no longer protected by the photoresist material and thereby define the desired features in the semiconductor wafer 10.
FIG. 2A depicts a more detailed view of the photoresist layer 18 subsequent to being patterned into a photoresist mask. In the process described above, the polymerized photoresist are removed, leaving photoresist lines 18a–d, which protect underlying layers from etching.
One important characteristic of the photoresist lines is known as an aspect ratio, which compares the vertical space between lines with the horizontal space. For example, the space between photoresist lines 18a and 18b would have an aspect ratio of approximately 1:2, while the space between photoresist lines 18b and 18c would have an 15 aspect ratio of about 5:2.
Each photoresist line 18a–d has a line width or critical dimension CD1, which determines the width of lines that will be etched in intermediate layers 15. Each photoresist line 18a–d also has a height, which is also known as a resist budget RB1. During the process of etching intermediate layers 15, photoresist lines 18a–d are also etched. Therefore, resist budget RB1 represents the amount of photoresist that may be consumed during the etching process. For ease of illustration, in FIGS. 2B–2D, only four photoresist lines 18a–d are shown, however, as is well known in the art, numerous photoresist lines 18a–d may be formed to produce the desired feature geometries. The feature geometries will in turn enable production of the electrical interconnections intended by the manufacturer, and enable the production of a functioning integrated circuit.
One technique that engineers use to increase the operating speeds of semiconductor devices is reducing the sizes of conductive lines within the semiconductor devices. Although much improvement has occurred in photolithography systems to enable the fabrication of small feature sizes, current lithographic tools are still unable to define feature sizes much below about 0.18 microns. Unfortunately, the costs of developing a photolithography system to define feature sizes below 0.18 microns would involve manufacturing of a new tool, and therefore would be prohibitively expensive. Thus, plasma etching has been considered as a method for further reducing the critical dimension CD1, which defines feature sizes of photoresist lines 18a–d. This technique is called photoresist trimming.
Typically, several shortcomings can be associated with the prior art photoresist trimming process. First, undesired tapering effect in photoresist lines are caused by photoresist trimming of photoresist lines in dense areas of photoresist lines. Second, photoresist trimming causes undesired resist budget reduction. Next, photoresist trimming results in a variation in critical dimensions of photoresist lines defined in different regions of the substrate wafer. The following is a brief description of the first limitation. The descriptions of the second and third drawbacks will follow immediately thereafter.
FIGS. 2B–2C illustrate the undesired tapering effect in photoresist lines resulting from prior art photoresist trimming in a densely packed areas of photoresist lines. FIG. 2B illustrates photoresist trimming of the patterned photoresist layer 18. As shown, after photolithography has been performed to produce photoresist lines 18a–d of, for example, about 0.18 microns, a plasma etch is performed to further reduce the critical dimensions of the photoresist lines 18a–d. Photoresist lines 18a–d are bombarded with an etchant flow 20/20′, such as oxygen ions, using a low RF bias power to create a plasma. As shown, etchant flow 20′ is distinguished from etchant flow 20 to illustrate ions traveling toward the photoresist lines 18a–d at somewhat variable angles.
As shown in FIG. 2B, the degree of exposure of each photoresist line 18e–g to the ion bombardment varies depending on the proximity of the photoresist line to that of other photoresist lines. If a photoresist line is located in an open area, the sidewalls of the photoresist line are in general, fully exposed to angled etchant flow 20′. However, if a photoresist line is located in a dense area, the amount of etchant flow 20′ that reaches the lower portions of photoresist sidewalls may be greatly reduced due to a large amount of etchant flow 20′ being blocked by the neighboring photoresist line.
For example, photoresist line 18a is isolated from other photoresist lines 18b–d. Therefore, photoresist lines 18b–d do not affect the exposure of photoresist line 18a to etchant flow 20′. However, because photoresist line 18c is located in close proximity to photoresist lines 18b and 18d, photoresist lines 18b and 18d block much of etchant flow 20′. For an etchant ion to reach the bottom of a sidewall of photoresist line 18c, it must either travel towards the sidewall at the perfect angle, or bounce from sidewall to sidewall as shown in FIG. 2B. The amount of etchant flow 20′ that reaches the sidewalls of photoresist lines 18b and 18d are likewise reduced by the close proximity of photoresist line 18d. 
FIG. 2C illustrates a prior art process of photoresist trimming that has been completed. As photoresist lines 18b–d are located in a dense area of photoresist lines, the top portions of photoresist lines 18b–d have been consumed much more rapidly by etchant flow 20/20′ than the bottom portions. Therefore, the sidewalls of photoresist lines 18b–d show an undesirable tapering effect, as opposed to critical dimension CD2, which is more uniform for photoresist line 18a. An ideal etch operation would leave vertical sidewalls in the surface of semiconductor wafer 10.
As the top of densely packed photoresist lines 18b–d has a higher horizontal etch or trim rate than the bottom, critical dimension CD of photoresist lines 18b–d at the top is less than critical dimension CD4 of photoresist lines 18b–d at the bottom. This variation in critical dimensions CD3 and CD4 may result in errors during etching of the intermediate layers 15 below photoresist layer 18. Such errors may in turn cause inconsistencies in the conductive lines formed during fabrication, therefore adversely effecting the speed and response time of the semiconductor device.
Another problem associated with the technique of photoresist trimming is that etchant flow 20/20′ significantly reduces resist budget RB1 of photoresist lines 18a–d as shown in FIG. 2A, to resist budget RB2, as shown in FIG. 2C. During etching the intermediate layers 15, photoresist lines 18a–d protect the portions of intermediate layers 15 defined below the photoresist lines 18a–18d, however during the process, the photoresist material itself will be etched away. Therefore, it is important to have an adequate resist depth or budget to ensure that there is enough photoresist material to prevent damage to the layers below. Because photoresist trimming reduces the resist budget of photoresist lines 18a–d, the process increases the chances that the layers below the photoresist material will be damaged due to insufficient resist budget.
Yet another problem associated with the prior art photoresist trimming process is forming photoresist lines having varied critical dimensions as a result of being defined in different regions of the substrate wafer. As illustrated in FIGS. 2D–2G, the prior art photoresist trimming process results in wafer substrates having non-uniform profiles. FIG. 2D, for example, shows a simplified cross sectional view of the semiconductor wafer 10. The semiconductor wafer 10 includes the substrate 12 configured to support the intermediate layers 15, which in one embodiment, includes the first layer 14 and the second layer 16. As illustrated, the semiconductor wafer 10 further includes the photoresist layer 18 used during the pattering and etching processes so as to form the features of the semiconductor devices. Different regions of the semiconductor wafer 10, such as a central region 10c and edge regions 11e2 and 10e1 have been marked accordingly and shown in FIG. 2D.
As described in more detail above, after depositing the layer of photoresist mask 18 over the intermediate layers 15, the photoresist layer 18 is patterned into the mask. Thereafter, the polymerized sections, formed as a result of exposing unmarked portions of the photoresist layer 18 to light, are removed leaving the photoresist lines 18e–18g, as shown in FIG. 2E. Each of the photoresist lines 18e–g is shown to respectively have critical dimensions CD5, CD6, and CD7 and the resist budget RB1. The critical dimension CD5, CD6, and CD7 and resist budge RB1 of the each of the corresponding photoresist lines 18e–g are expected to be the same irrespective of the location of the photoresist lines 18e–g. Simply stated, it is expected that the photoresist line 18e and 18g defined in the edge regions 10c2 and 10c1 and the photoresist line 18f defined in the center region 10c of the semiconductor wafer 10 to have the same critical dimension and resist budget. It must be noted that for ease of illustration and reference, only one photoresist line is shown in each of the edge region 10e2 and 10e1 and the center region 10c (18e and 18g and 18f, respectively). However, as is well known in the art, numerous photoresist lines 18e–18g can be formed in each of the edge and center regions of the semiconductor wafer so as to produce the desired feature geometries.
FIG. 2F depicts the prior art Photoresist trimming of the photoresist lines 18e–g using the plasma etching. The photoresist lines 18e–g are bombarded with the etchant flow 20 so as to equally reduce the critical dimension of each photoresist line 18e–g. However, at the conclusion of the prior art photoresist trimming process, the critical dimensions and photoresist budgets of the photoresist lines 108e–g is shown to vary throughout the semiconductor wafer 10, as shown in FIG. 2G. The photoresist lines 18e and 18g, respectively defined in the edge regions 10e2 and 10e1 are shown to respectively have critical dimensions CD5′ and CD7′, each of which is less than the corresponding initial critical dimension CD5 and CD7. In a like manner, photoresist lines 18e and 18g are shown to have a reduced resist budge RB2e. Similarly, the photoresist line 18f, defined in the center region 10c of the semiconductor wafer 10 is also shown to have a reduced critical dimension CD6′ and resist budget RB2c. However, comparatively, the critical dimension CD6′ of the photoresist line 18f is shown to be substantially less than the critical dimensions CD5′ and CD7′ of respective photoresist lines 18e and 18g. Similarly, the resist budget RB2c of the photoresist line 18f is substantially less than the resist budget RB2e of the photoresist lines 18e and 18g. 
Producing of photoresist lines with varied and inconsistent critical dimensions can be understood with reference to the prior art etching operation performed in the etch chamber 52, as shown in FIG. 2H. The semiconductor wafer 10 is placed on a bottom chuck 54 defined in the etch chamber 52. The illustrated bottom chuck 54 and a top chuck 56 are respectively connected to a bottom RF power 66 and top RF power 64. Residue resulting from the etching operation is configured to be purged using a plurality of exhaust pipes 62.
As shown, an etchant gas 68 defined in an etchant container 58 is introduced into the etch chamber 52 using a nozzle 60 defined in the very center of the top chuck 56. As shown, a concentration of a center etchant flow 20c is greater than the concentration of an edge etchant flow 20e. Thus, as illustrated, depending on being defined in the center region 10c as opposed to the edge regions 10e1 and 10e2 of the semiconductor wafer 10a, the photoresist lines are exposed to a different degree of etchant. That is, the photoresist lines 18e and 18g are exposed to the edge etchant flow 20e which concentration of etchant flow is substantially lower than the concentration of the center etchant flow 20f applied to the photoresist line 18f defined in the center 10c. As a result, a top portion of the photoresist line 18f is exposed to a greater concentration of the etchant flow 20c, causing the photoresist line 18f to be consumed more rapidly. Thus, generally, the critical dimension and resist budget of the photoresist lines defined in the center region are substantially less than the critical dimension and resist budget of the photoresist lines defined in the edge regions of the semiconductor substrate. The variation in the critical dimensions CD5′ through CD7′ is disfavored as it can result in errors during etching of the intermediate layers 15 defined below the photoresist layer 18. As described above, these errors adversely effect the speed and response time of the semiconductor devices. As to the reduced resist budget, the prior art increases chances of damaging the intermediate layers 15 due to having insufficient resist budget.
Despite the development of photoresist trimming and the growing need for semiconductor devices with very small and conductive lines, a reliable method for preventing the tapering of photoresist lines in dense areas, preserving photoresist budget, and preventing formation of non-uniform critical dimension is not available. In view of the foregoing, there is a need for a reliable method for trimming photoresist material from photoresist lines in semiconductor wafers while maintaining critical dimensions of the photoresist lines consistent throughout the semiconductor wafer and maximizing the resist budget of each line.